The present invention relates to an apparatus and method for designing circuits. More specifically, the invention relates to instantiating one or more leaf cells using a customizable syntax which differs from the fixed or given syntax used to instantiate a single leaf cell.
Electronic components are becoming increasingly complex as more and more capability is being designed into the electronic components. Typically, the more complex an electrical component becomes, the greater number of semiconductor devices that need to be used to form the circuits that carry out the functions.
In the past, circuits were designed from scratch. The circuits were designed using a graphical tool to draw schematic diagrams of the circuits. Designers use a graphical program, such as Composer which is available from Cadence, Inc. of San Jose, Calif. Drawing the schematic is actually a graphical process in which the designer uses symbols to designate one of various types of transistors, such as for an NMOS or PMOS transistor. A number of transistors are designated with the transistor type, and then a wiring feature is used to connect terminals of all the designated devices together. The designer provides input ports and output ports and annotates the symbols to specify certain properties for a particular transistor. The properties specified include length and width of a gate of a transistor. Other size properties may also be designated. In short, past efforts for circuit design include a graphical way of trying to describe the particular components and the way the components are connected.
Before actually building the circuit, several tests are performed on the circuit as designed. The first test is a functional simulation. The functional simulation attempts to assure that the design of the circuit is correct. In other words, for a certain set of inputs, the circuit should produce a certain set of outputs in order for the circuit to be correctly carrying out a function. A first series of scripts or procedures are applied to the graphical data used to design the circuit. The series of scripts or procedures converts the graphical data to a hardware description language (xe2x80x9cHDLxe2x80x9d). One commonly used HDL is known as Verilog. Once the HDL is formed, a simulation program, such as VCS Simulator available from Synopsis of Mountain View, Calif. is used to test the functionality of the circuit. Verilog is a HDL that is used to interconnect the blocks for the purpose of running a functional simulation test.
Another trend is to design at least some portions of a circuit from certain building blocks (called leaf cells) which include a group of transistors. Rather than design a circuit totally from scratch, the circuit is designed by connecting these building blocks or leaf cells. This trend is valuable especially since circuits have increasingly become much more complex. In designing the circuit, a designer sets out the parameters for a leaf cell and also sets out the connections to other leaf cells which comprise a portion of the circuit. Circuit designers can now design circuits more quickly since certain functions are already designed in blocks or leaf cells. A major portion of the circuit design can be accomplished by linking the various leaf cells. The resulting circuit designs can be accomplished more quickly. Furthermore, the calling up of set leaf cells prevents or makes mistakes less likely in the leaf cells.
Calling up a leaf cell includes designating the type of leaf cell, the parameters to be associated with the leaf cell and designating the connections to the various inputs and outputs of the leaf cell. Providing the parameters and providing the connections to the leaf cell is called instantiation. To instantiate leaf cells to describe the variables associated with the leaf cell and to describe the interconnections between leaf cells circuit designers use a very specific syntax and semantics. For example, Verilog is one program used to call up leaf cells and instantiate them in a circuit and produce HDL for the circuit. In Verilog, there are typically two methods of instantiation. One instantiation method requires the designer to use a specific set of symbols that represent an ordered connection. The first method of instantiation, is based on the order of the various symbols. The designer has to know the order of the symbols for calling a particular macro in Verilog. In Verilog, for example, the output is listed first and then the particular pin associated with the output. The second method of instantiation in Verilog is to designate a pin based connection. In the pin based connection type of instantiation, the designer calls out the pin. After calling out the pin, the designer designates the net connected to the pin in parenthesis.
The current methods of instantiation of an HDL have problems. Among the problems are that the designer had to use a fixed syntax in order to instantiate a leaf cell in a design. The designer must know what that order is and then the nets to match that order. If the specific syntax is not used, errors arise which need to be corrected later before a proper and accurate simulation can be accomplished. In other words, there is no option for customizing or for a user to provide his or her own syntax for instantiating leaf cells. Another problem is that when a cell has a large number of input/output pins, there is a relatively large margin for errors which can slow down the design of a circuit using the leaf cells. Still a further disadvantage is that the fixed syntax does not have the capability to call more than a single leaf cell.
A method of instantiating a leaf cell having various connections and designed to be called using a fixed syntax includes defining a template syntax different from the fixed syntax, setting default values for connections not designated by the template syntax, and mapping the template syntax to a hardware design language. The hardware design language describes the leaf cell. The description of the leaf cell has values for the designated connections and non-designated connections. The non-designated connections have the default values. The method also includes calling a leaf cell using the template syntax. When using the template syntax, in some embodiments, less than all the connections are designated. Variables may also be set in the template syntax to reference positional nets matching the leaf cell called. In some embodiments, the hardware design language describing the leaf cell is a Verilog statement. In other embodiments, the method further includes defining a second template syntax different than the first template syntax and the fixed syntax. The second template syntax instantiates the same leaf cell as the first template syntax or the fixed syntax.
The invention also includes an article of manufacture comprising a computer readable media having instructions thereon for causing a suitably programmed system to execute the method of instantiating a leaf cell having various connections and designed to be called using a fixed syntax includes defining a template syntax different from the fixed syntax, setting default values for connections not designated by the template syntax, and mapping the template syntax to a hardware design language.
Also disclosed is a method of instantiating a leaf cell having various connections and designed to be called using a fixed syntax, the method includes defining a first template syntax different from the fixed syntax, and defining a second template syntax different from the fixed syntax and different from the first template syntax. The method also includes mapping the first template syntax and the second template syntax to a hardware design language describing the leaf cell in which designated connections have values. Default values are set for connections not designated by the first template syntax. The method further includes setting default values for connections not designated by the first template syntax; and setting default values for connections not designated by the second template syntax. In one embodiment, the leaf cell is called using the first template syntax. Variables are set to reference positional nets matching the leaf cell called. In another embodiment, the leaf cell is called using the second template syntax. In some embodiments, the hardware design language describing the leaf cell is a Verilog statement. Also disclosed is an article of manufacture including a computer readable media having instructions thereon for causing a suitably programmed system to execute the method of instantiating a leaf cell having various connections and designed to be called using a fixed syntax, the method includes defining a first template syntax different from the fixed syntax, and defining a second template syntax different from the fixed syntax and different from the first template syntax, and mapping the first template syntax and the second template syntax to a hardware design language describing the leaf cell in which designated connections have values.
Another method is for instantiating a plurality of leaf cells having various connections. The leaf cells are designed to be called separately using a fixed syntax. The method defines a template syntax different from the fixed syntax. The template syntax defines a first leaf cell and a second leaf cell, and maps the template syntax to a hardware design language describing the first leaf cell and the second leaf cell and the connections to one another. This method also includes setting default values for connections not designated by the template syntax for the first leaf cell, and setting default values for connections not designated by the template syntax for the second leaf cell. In addition, the method also includes designating default values for the first leaf cell and the second leaf cell for connections not designated by the template syntax.